View KAI-1020-CBA-FD-BA_7177140.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

device performance specification revision 5.0 mtd/ps-0205 january 29, 2007 kodak kai-1020 image sensor 1000 (h) x 1000 (v) interline transf er progressive scan ccd
contents summary specification ............................................................................................................................................................... 5 description ..................................................................................................................................................................................5 features .......................................................................................................................................................................................5 applications .................................................................................................................................................................................5 ordering information .................................................................................................................................................................. 6 device description ...................................................................................................................................................................... 7 architecture .................................................................................................................................................................................7 physical description ....................................................................................................................................................................8 pin description and device orientation ..................................................................................................................................8 imaging performance ............................................................................................................................... ................................ 11 optical specification ............................................................................................................................... ...................................11 ccd specifications ............................................................................................................................... .....................................11 cds output specification ............................................................................................................................... ...........................11 general ? monochrome ............................................................................................................................... .............................11 general color ............................................................................................................................... .............................................11 power .........................................................................................................................................................................................12 typical performance curves ............................................................................................................................... ...................... 13 monochrome quantum efficiency ............................................................................................................................... .............13 color quantum efficiency ............................................................................................................................... ..........................13 photoresponse vs. angle ............................................................................................................................... ...........................14 sensor power ............................................................................................................................... .............................................14 frame rate ............................................................................................................................... .................................................15 defect definitions ............................................................................................................................... ....................................... 17 specifications ............................................................................................................................... .............................................17 test definitions ............................................................................................................................... .......................................... 18 test conditions ............................................................................................................................... ...........................................18 tests ...........................................................................................................................................................................................18 test regions of interest ............................................................................................................................... .............................21 operation ............................................................................................................................... .................................................... 25 single or dual output ............................................................................................................................... .................................25 the kai-1020 pixel ............................................................................................................................... .....................................26 high level black diagram ............................................................................................................................... .........................27 main timing ............................................................................................................................... ................................................28 vertical frame timing ............................................................................................................................... ................................28 horizontal line timing ............................................................................................................................... ...............................29 single output ............................................................................................................................... ..........................................31 dual output ............................................................................................................................... .............................................31 electronic shutter ............................................................................................................................... ......................................32 substrate voltage ............................................................................................................................... ...................................32 substrate voltage and antiblooming ............................................................................................................................... .....32 electronic shutter timing ............................................................................................................................... ......................32 fast dump ............................................................................................................................... ..................................................33 binning and interlaced modes ............................................................................................................................... ...................35 correlated double sampling (cds) ............................................................................................................................... ...........36 cds timing edge alignment ............................................................................................................................... ..................36 disabling the cds ............................................................................................................................... ...................................37 timing and voltage specifications ............................................................................................................................... .............38 absolute maximum ratings ............................................................................................................................... ...................38 ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p2
timing ............................................................................................................................... .....................................................38 bias voltages ............................................................................................................................... ..........................................38 power up sequence ............................................................................................................................... ...............................38 pulse amplitudes ............................................................................................................................... ...................................39 timing examples ............................................................................................................................... ........................................40 progressive scan ............................................................................................................................... ....................................40 fast line dump ............................................................................................................................... ......................................41 interlaced ? field integration ............................................................................................................................... .................42 camera design ............................................................................................................................... ........................................... 43 low level block diagram ............................................................................................................................... ............................43 horizontal ccd drive circuit ............................................................................................................................... .....................44 vertical ccd ............................................................................................................................... ...............................................45 electronic shutter ............................................................................................................................... ......................................46 cds timing inputs ............................................................................................................................... ......................................47 cds output circuit ............................................................................................................................... ......................................47 power supplies ............................................................................................................................... ...........................................48 kai-1020 evaluation board ............................................................................................................................... ........................ 49 front side ............................................................................................................................... ....................................................49 back side ............................................................................................................................... ....................................................50 schematics ............................................................................................................................... .................................................51 kai-1020 ............................................................................................................................... ..................................................51 timing logic ............................................................................................................................... ...............................................52 output 1 ............................................................................................................................... ...................................................53 output 2 ............................................................................................................................... ...................................................54 automatic offset and power supply ............................................................................................................................... .......55 parts list ............................................................................................................................... ....................................................56 digital output connector ............................................................................................................................... ............................57 power connector ............................................................................................................................... ........................................58 mode switch ............................................................................................................................... ...............................................58 exposure switch ............................................................................................................................... .........................................59 substrate voltage trim ............................................................................................................................... ..............................59 evaluation board notes ............................................................................................................................... .............................59 timing ............................................................................................................................... .....................................................59 output channel ............................................................................................................................... .......................................60 automatic offset ............................................................................................................................... .....................................60 oscilloscope traces ............................................................................................................................... ...................................61 cds timing ............................................................................................................................... .............................................61 vertical retrace ............................................................................................................................... ......................................62 horizontal retrace ............................................................................................................................... .................................63 storage and handling ............................................................................................................................... ................................ 64 esd ............................................................................................................................................................................................64 cover glass care and cleanliness ............................................................................................................................... ............64 environmental exposure ............................................................................................................................... ............................64 mechanical drawings ............................................................................................................................... ................................. 65 completed assembly ............................................................................................................................... .................................65 pin grid array ............................................................................................................................... .........................................65 leadless chip carrier ............................................................................................................................... ............................66 leadless chip carrier and soldering ............................................................................................................................... ....66 cover glass ............................................................................................................................... .................................................67 ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p3
pin grid array cover glass ............................................................................................................................... .....................67 leadless chip carrier cover glass ............................................................................................................................... ........68 glass transmission ............................................................................................................................... ................................69 quality assurance and reliability ............................................................................................................................... .............. 70 quality strategy ............................................................................................................................... ..........................................70 replacement ............................................................................................................................... ..............................................70 liability of the supplier: ............................................................................................................................... .............................70 liability of the customer ............................................................................................................................... ............................70 reliability ............................................................................................................................... ....................................................70 test data retention ............................................................................................................................... ....................................70 mechanical ............................................................................................................................... ..................................................70 warning: life support applications policy ............................................................................................................................... 70 revision changes ............................................................................................................................... ....................................... 71 table of figures figure 1: test sub regions of interest ............................................................................................................................... ..........21 figure 2: regions of interest ............................................................................................................................... .........................22 figure 3: center region of interest ............................................................................................................................... ...............23 figure 4: zones 1 and 2 ............................................................................................................................... ..................................24 ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p4
summary specification kodak kai-1020 image sensor 1000 (h) x 1000 (v) progressive scan interline ccd image sensor description the kodak kai-1020 image sensor is a one megapixel interline ccd with integrated clock drivers and on-chip correlated double sampling. the progressive scan architecture and global electronic shutter provide excellent image quality for full motion video and still image capture. the integrated clock drivers allow for easy integration with cmos logic timing generators. the sensor features a fast line dump for high-speed sub-window readout and single (30 fps) or dual (48 fps) output operation. features ? 10 bits dynamic range at 40 mhz ? large 7.4 m square pixels for high sensitivity ? progressive scan (non-interlaced) ? integrated vertical clock drivers ? integrated correlated double sampling (cds) up to 40 mhz ? integrated electronic shutter driver ? reversible hccd capable of 40mhz operation all timing inputs 0 to 5 volts ? single or dual video output operation ? progressive scan or interlaced ? fast dump gate for high speed sub-window readout ? antiblooming protection applications ? industrial imaging ? medical imaging parameter typical value architecture interline ccd, progressive scan total number of pixels 1028 (h) x 1008 (v) number of effective pixels 1004 (h) x 1004 (v) number of active pixels 1000 (h) x 1000 (v) pixel size 7.4 m (h) x 7.4 m (v) active image size 7.4 mm (h) x 7.4 mm (v) 10.5 mm (diagonal) aspect ratio 1:1 number of outputs 1 or 2 saturation signal 40,000 electrons output sensitivity 12 v/electron quantum efficiency kai-1020-aba (500nm) 44% quantum efficiency kai-1020-cba r(620nm), g(54 0nm), b(460nm) 31%, 36%, 41% dark noise 50 electrons rms dark current (typical) <0.5 na/cm 2 dynamic range 58 db blooming suppression 100 x image lag <10 electrons smear <0.03% maximum data rate 40 mh z/channel (2 channels) frame rate progressive scan, one output progressive scan, dual outputs interlaced scan, one output 30 fps 48 fps 49 fps integrated vertical clock drivers integrated correlated double sampling (cds) integrated electronic shutter driver package 68 pin pga or 64 pin clcc cover glass ar coated, 2 sides all parameters above are specified at t = 40 c ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p5
ordering information catalog number product name de scription marking code 2h4889 kai- 1020-aaa-jp-ba monochrome, no microlens, pga package, taped clear cover glass, no coatings, standard grade kai-1020 serial number 4h0934 kai- 1020-abb-fd-ae monochrome, telecentric microlens, clcc package, clear cover glass with ar coating (both sides), engineering sample 4h0933 kai- 1020-abb-fd-ba monochrome, telecentric microlens, clcc package, clear cover glass with ar coatin g (both sides), standard grade 4h0932 kai- 1020-abb-jb-ae monochrome, telecentric microlens, pga package, clear cover glass (no coatings), engineering sample 4h0931 kai- 1020-abb-jb-ba monochrome, telecentric microlens, pga package, clear cover glass (no coat ings), standard grade 4h0910 kai- 1020-abb-jd-ae monochrome, telecentric microlens, pga package, clear cover glass with ar coating (both sides), engineering sample 4h0935 kai- 1020-abb-jd-ba monochrome, telecentric microlens, pga package, clear cover glass with ar coatin g (both sides), standard grade kai-1020-abb serial number 2h4996 kai- 1020-cba-fd-ae color (bayer rgb), telecentric microlens, clcc package, clear cover glass with ar coating (both sides), engineering sample 4h0131 kai- 1020-cba-fd-ba color (bayer rgb), telecentric microlens, clcc package, clear cover glass with ar coatin g (both sides), standard grade 4h0194 kai- 1020-cba-jd-ae color (bayer rgb), telecentric microlens, pga package, clear cover glass with ar coating (both sides), engineering sample 4h0193 kai- 1020-cba-jd-ba color (bayer rgb), telecentric microlens, pga package, clear cover glass with ar coatin g (both sides), standard grade kai-1020cm serial number 1e9790 kek-1e9790-kai-1020- 12-40 evaluation board (complete kit) n/a please see iss application note ?product naming convention? (mtd/ps-0892) for a full description of naming convention used for kodak image sensors. address all inquiries and purchase orders to: image sensor solutions eastman kodak company rochester, new york 14650-2010 phone: (585) 722-4385 fax: (585) 477-4947 e-mail: imagers@kodak.com kodak reserves the right to change any in formation contained herein without notice. all information furnished by kodak is believed to be accurate. ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p6
device description architecture 1000 (h) x 1000 (v) active pixels g g r b g g r b g g r b g g r b 4 dark rows 12 dark columns 12 dark columns vout1 vout2 2 buffer columns 2 buffer columns 2 buffer rows 2 buffer rows pixel 1,1 dual output or 8 12 2 1000 2 12 8 single 8 12 2 500 500 2 12 8 fast line dump 8 empty pixels 8 empty pixels there are 4 light shielded rows followed 1004 photoactive rows. the first 2 and the last 2 photoactive rows are buffer rows giving a total of 1000 lines of image data. in the single output mode all pixels are clocked out of the video 1 output in the lower left corner of the sensor. the first 8 empty pixels of each line do not receive charge from the vertical shift register. the next 12 pixels receive charge from the left light-sh ielded edge followed by 1004 photo-sensitive pixels and finally 12 more light shielded pixels from the right edge of the sensor. the first and last 2 photosensitive pixels are buffer pixels giving a total of 1000 pixels of image data. in the dual output mode the clocking of the right half of the horizontal ccd is reversed. the left half of the image is clocked out video 1 and the right half of the image is clocked out video 2. each row consists of 8 empty pixels followed by 12 light shielded pixels followed by 502 photosensitive pixels. when reconstructing the image, data from video 2 will have to be reversed in a line buffer and appended to the video 1 data. ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p7
physical description pin description and device orientation pin grid array when viewed from the top with the pin 1 index to the upper le ft, the center of the photoactiv e pixel array is offset 0.006" above the physical center of the package. the pin 1 index is located in the corner of the package above pins l2 and k1. when operated in single output mode the first pixel out of the sensor will be in the corner closest to vout1b (pin l9). the hccd is parallel to the row of pins a10 to l10. in the pictures below, the v ccd transfers charge down. ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p8
pin grid array pin description r2 c11 s2b d11 h1br e11 h1s f11 gnd g11 h2bl h11 s1a j11 t1 k11 t2 b11 vdd l10 vout2b a10 s2a c10 h2br d10 gnd e10 h2s f10 h1bl g10 s1b h10 r1 j10 k10 vdd b10 c1 d1 e1 f1 g1 h1 j1 k1 b1 vsub l2 v1in a2 c2 d2 e2 f2 g2 h2 j2 v2in k2 b2 gnd b9 vdd b8 v1s5 b7 v1out b6 v1low b5 shc2 b4 sh b3 vout2a a9 v1 a8 v1mid a7 a6 shd1c1 a5 shc1 a4 vsh15 a3 gnd k9 vdd k8 v2b k7 v2s9 k6 v2a k5 v2mid k4 v2low k3 vout1b l9 vout1a l8 fd l7 v2s5 l6 vsub l5 v2high l4 v2out l3 pin 1 index top view label pin function label pin function v2in k2 vccd gate phase 2 input h1s f11 hccd storage phase 1 clock input vsub l2 substrate voltage input gnd e10 ground (0v) v2low k3 vccd phase 2 clock driver low h1br e11 hccd right phase 1 barrier clock input v2out l3 vccd phase 2 clock driver output h2br d10 hccd right phase 2 barrier clock input v2mid k4 vccd phase 2 clock driver mid s2b d11 video 2 cds sample b clock input v2high l4 vccd phase 2 clock driver high s2a c10 video 2 cds sample a clock input v2a k5 vccd phase 2 clock driver input a r2 c11 video 2 cds reset clock input vsub l5 substrate voltage input t2 b11 video 2 cds transfer clock input v2s9 k6 vccd phase 2 cl ock driver +9v vdd2 b10 video 2 cds +15v v2s5 l6 vccd phase 2 clock driver +5v fast dump clock driver +5v vout2b a10 video 2 cds output b v2b k7 vccd phase 2 clock driver input b gnd b9 ground (0v) fd l7 fast dump clock driver input vout2a a9 video 2 cds output a vdd1 k8 video 1 cds +15v vdd2 b8 video 2 cds +15v vout1a l8 video 1 cds output a v1 a8 vccd phase 1 clock driver input gnd k9 ground (0v) v1s5 b7 vccd phase 1 clock driver +5v vout1b l9 video 1 cds output b v1mi d a7 vccd phase 1 clock driver mid vdd1 l10 video 1 cds +15v supply v1out b6 vccd phase 1 clock driver output t1 k11 video 1 cds transfer clock input v1low b5 vccd phase 1 clock driver low r1 j10 video 1 cds reset clock input shd1c1 a5 shutter driver connection s1a j11 video 1 cds sample a clock input shc2 b4 shutter driver connection s1b h10 video 1 cds sample b clock input shc1 a4 shutter driver connection h2bl h11 hccd left phase 2 barrier clock input sh b3 shutter driver clock input h1bl g10 hccd left phase 1 barrier clock input vsh15 a3 shutter driver +15v gnd g11 ground (0v) v1in a2 vccd gate phase 1 input h2s f10 hccd storage phase 2 clock input all pins not listed must be unconnected. ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p9
leadless chip carrier 11 6 17 64 32 33 48 49 8 24 40 56 v2in vsub v2low v2out v2mid v2high v2a n/c v2s9 v2s5 v2b fd vdd vout1a gnd vout1b vdd t1 r1 s1a s1b h2bl h1bl gnd h2s h1s gnd h1br h2br s2b s2a r2 t2 vdd vout2b gnd vout2a vdd v1 v1mid v1s5 v1low shd1c1 shc2 shc1 v1out sh vsh15 v1in n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c n/c top view pin descri ption de pti pin scri on 1 v2in h2 25 s 2 vsub h1 26 s 3 v2low gn 27 d 4 v2out h1 28 br 5 v2mid h2 29 br 6 v2high s2 30 b 7 v2a s2a 31 8 no connect r2 32 9 v2s9 t2 33 10 v2s5 vdd 34 11 v2b vo 35 ut2b 12 fd gn 36 d 13 vdd vo 37 ut2a 14 vout1a vdd 38 15 g nd v1 39 16 vout1b v1 40 s5 17 vdd v1 41 mid 18 t1 v1 42 out 19 r1 v1 43 low 20 s1a sh 1 44 d1c 21 s1b sh 45 c2 22 h2bl sh 46 c1 23 h1bl sh 47 24 gnd 48 vsh15 50-64 no connect 49 v1in ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p10
imaging performance optical specification symbol description min. nom. max. units notes sampling plan qe max peak quantum efficiency 42 45 % 1 design qe peak quantum efficiency wavelength 490 nm 1 design qe h microlens acceptance angle (horizontal) 12 13 degrees 2 design qe v microlens acceptance angle (vertical) 25 30 degrees 2 design qe(540) quantum efficiency at 540nm 38 40 % 1 design pnu photoresponse nonuniformity 5 % design nl maximum photoresponse nonlinearity 2 % 3, 4,18 die g maximum gain difference between outputs 10 % 3, 4,18 die nl maximum signal error caused by nonlinearity differences 1 % 3, 4,18 die dark center uniformity 12 e - rms 19, 20 die dark global uniformity 2 mvpp 19, 20 die global uniformity 5 %rms 19, 20 die global peak to peak uniformity 15 %pp 19, 20 die center uniformity 0.7 %rms 19, 20 die ccd specifications symbol description min. nom. max. units notes sampling plan vne vertical ccd charge capacity 54 60 ke - design hne horizontal ccd charge capacity 110 120 ke - design pne photodiode charge capacity 38 42 ke - 5 die id dark current 0.2 0.5 na/cm 2 6 die lag image lag < 10 50 e - 7 design xab antiblooming factor 100 300 1, 8, 9, 10, 11 design smr vertical smear 72 db design -75 - 1, 8, 9 cds output specification symbol description nominal un its n otes sampling plan p d power dissipation 213 m 12 de w sign f -3db bandwidth 140 mhz 2 de 1 sign c l max off-chip load 10 p 13 de f sign a v gain 0.70 de 12 sign v/ n sensitivity 13 v 12 de / e - sign r output impedance 160 12 de sign vsat saturation voltage 500 m 5, 12 d v ie iout output bias current 3.0 m de a sign general ? monochrome symbol description nomi un nal its no tes sampling plan n e-t total camera noise 42 e - r 6, 14 design ms dr dynamic range 60 db 15 desi gn general color symbol description nomi un nal its notes sampling plan n e-t total camera noise 50 e - r 6, 14 design ms dr dynamic range 58 d desi b 15 gn ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p11
power description nomina l units notes single channel cds 213 mw 12 vccd clock d mw 16 river 71 electr onic sh mw utter driver 1.1 hccd 17 122 mw 16, total p ower 6 407 mw 12, 1 no 1. sured 2. lue is th h the quantum efficiency is at least qemax at a wavelength angles are measured th respe allel to the horizontal axis ( qeh) or in a plane para to the axis ( qev). 3. ue is ov 4. e is fo 5. this value g. higher photodiode saturation charge ca pac will ant g specifica substrate ith each part for 42 ke - . 6. measured 7. this is the tion. measured by strobe illumination of the device at 70% of p ode s nd then uring the subseq e pixel output in the dark. 8. measured with a spot size of 100 ve rtical pixels, no electronic shutter. nm to 580 nm). d as when the spot size doubles in size. 11 m light intensity whic s g b t in ich f otodiodes. 12. u 13. th total pf een the outputs and ac ground. 14 ludes er e a rk cur nt sho ise at 40 mhz. total noise m on the ka i-1020 evaluation rd. 15. ses 20l 16 30 fram le output 17 is inclu xternal hccd driv 18 the sa asured at 10 mhz 19. tested at 27 and 40 c sa a sa pling pl die? i tes ever vice is ainst the specified performance limits. sampling plan defined gn? indicate sam test charact n, at the discretion of kodak, against the specified pe rmanc tes: mea with f/4 imaging optics. va e angular range of incident light for whic 50% of of qe. wi ct to the sensor surface normal in a plane par llel vertical val valu er the range of 10% to 90% of photodiode saturation. out binning. r the sensor operated with depends on the substrate voltage settin ities lower the ibloom in tion. voltage will be specif ied w at 40oc, 40 mhz hc cd frequency. first field decay lag at 70% satura hotodi atu ration, a meas uent frame?s averag 9. measured with green light (500 10. a blooming condition is define . antibloo o ing factor is the h cause bloom in divided y the ligh tens ity wh irst saturates the p h single wi tput power, 3ma load output load capacitance of c = l 10 system electronics noise, dark patt betw . inc n nois nd da re t no easured boa u og(pne/n e-t ) . at es/sec, sing . th des the power of the e clock er. . for mpling plan, me 20. see tests mpling pl n m an defined as ? ndica that y de verified ag as ?desi s a pled or e rizatio rfo e limits. ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p12
typical performance curves m me qua onochro ntum e fficie ncy 0.00 0.05 0.10 0.15 0.20 0.25 absolute quantum 0.30 0.35 0.40 0.45 0.50 600 700 800 900 1000 without cover glass efficiency without cov 300 400 500 wavelength (nm) er glass, without microlens color quantum efficiency kai-1020cm quantum efficiency 0 5 10 15 20 25 30 35 40 45 350 400 450 500 550 600 650 700 750 800 850 900 950 1000 wavelength (nm) quantum efficiency red green blue ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p13
photoresponse vs. angle ka 110 i1020 photoresponse vs. angle 0 10 20 30 40 50 60 70 80 90 100 -35 -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 35 angle (degrees) photoresponse (relative) horizontal vertical the horizontal curve is where the incident light an gle is varied in a plane parallel to the hccd. e is varied in a plane perpendicular to the hccd. sensor power the vertical curve is where the incident light angl kai-1020 power (single output) 0 100 200 300 400 500 0 5 10 15 20 25 30 frames/sec power (mw) hccd vccd total power ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p14
frame rate frame rate (1000 x 1000 pixels) 0 10 20 30 40 50 0 5 10 15 20 25 30 35 40 pixel frequency (mhz) frames/sec dual output single output frame rate (75% subsample 1000 x 750 pixels) 0 10 20 30 40 50 60 0 5 10 15 20 25 30 35 40 pixel frequency (mhz) frames/sec single output dual output frame rate (50% subsample 1000 x 500 pixels) 0 10 20 30 40 frames 50 60 70 80 0 5 10 15 20 25 30 35 40 pixel frequency (mhz) /sec frame rate (25% subsample 1000 x 250 pixels) 0 20 40 100 0 5 10 15 20 25 30 35 40 pixel frequency (mhz) frames/sec 80 single output dual output 60 dual output single output ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p15
frame rate (1000 x 1000 pixels) interlaced 0 10 20 30 40 50 60 70 80 0 5 10 15 20 25 30 35 40 pixel frequency (mhz) frames/sec dual output single output ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p16
defect definitions specifications name definition maximum temperature(s) tested at (c) notes test sampling plan dark field major bright defective pixel defect >= 28mv 1 6 die bright field major dark or bright defective pixel defect >= 11% 10 27, 40 7 die bright field minor dark defective pixel defect >= 5% 20 in zone 2 27, 40 8 8 die dark field minor bright defective pixel defect >= 14mv 100 27, 40 2 6 die bright field dead dark pixel defect >= 40% 0 27, 40 5 7 die bright field nearly dead dark pixel defect >= 20% 0 in zone 1 1 in zone 2 27, 40 5, 8 7 die dark field saturated bright pixel defect >= 106mv 0 27, 40 3 6 die dark field minor cluster defect a group of 2 to 10 contiguous dark field minor defective pixels 0 27, 40 4 die bright field minor cluster defect a group of 2 to 10 contiguous bright field minor defective pixels 2 in zone 2 27, 40 4, 8 die major cluster defect a group of 2 to 10 contiguous major defective pixels 0 27, 40 4 die column defect a group of more than 10 contiguous major defective pixels along a single column 0 27, 40 die column average magnitude within +/-0.4% of regional average (5 columns) 0 27, 40 6, 7 9 die notes: 1. the defect threshold was determined by using a threshold of 8mv at an integration time of 33 milliseconds and scaling it by the actual integration time used of 117 msec. 8mv*(117 msec/ 33 msec) = 28 mv 2. the defect threshold was determined by using a threshold of 4mv at an integration time of 33 milliseconds and scaling it by the actual integration time used of 117 msec. 4mv*(117 msec/ 33 msec) = 14 mv 3. the defect threshold was determined by using a threshold of 30mv at an integration time of 33 milliseconds and scaling it by the actual integration time used of 117 msec. 30mv*(117 msec/ 33 msec) = 106 mv 4. the maximum width of any cluster defect is 2 pixels. 5. only dark defects. 6. local average is centered on column. 7. see test regions of interest for region used. 8. see figure 4 for zone 1 and 2 definitions. defect map the defect map supplied with each sensor is based upon testin g at an ambient (27c) temper ature. minor point defects are not included in the defect map. all defective pixels are referenced to pixel 1,1 in the defect map (see figure 2: regions of interest ). ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p17
test definitions test conditions tion condition notes descrip frame time 117 msec 1 horizontal clock frequency 10 mhz light source (led) continuous green illumination centered at 530 nm 2 operation nominal operating voltages and timing notes: 1. electronic sh 2. utter is not als frame time. green led used : n em conversion s er electron eas ystem gain (calcu r adu 1. dark field center un st is perfo tions. only th e center 1 100 pixels o the sensor are u for this ls 431,43 e 3: center region of interest . used. integration time equ ichia nspg500s. test syst factors kai-1020m output sen itivity: 13 v p test system gain (m test s ured): 0.25 mv per adu la ted): 19 electrons pe tests iformity rmed under dark field condi this te 00 by f sed test (pixe 1 to pixel 530,530). see figur ? ? ? ? ? ? ? = time nintegratio dps * electrons in pixels 100 by 100 center of deviation standard uniformity center field dark ? used time nintegratio actual d erformance sp ecification integration time = 33 msec 2. nditions. the sensor is partitioned into 100 sub regions of interest, each of 00 pixels in size. see figure 1: test sub regions of interest . the average signal level of each of the calculated. the signal level of each of the sub regions of interest is calculated using adu ? horizo ntal overclock average in adu) * mv per count re i = 1 to 100. during this calculation on the 100 sub regions of interest, the maximum and minimum signal e dark field global uniformity is th en calculated as the maximum signal found minus the minimum signal level units: mvpp (millivolts peak to peak) units: e- rms ps integration time: device p dark field global un iformity this test is performed under dark field co which is 100 by 1 100 sub regions of interest is the following formula: signal of roi[i] = (roi average in whe levels are found. th found. ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p18
3. global uniformity this test is perform ed with the light source illuminated to a level such that the output of the sensor is at 70% of 364 mv). prior to this test being performed the substrate voltage has been set such that ty of the sensor is 520mv. global uniform ity is defined as: saturation (approximately the charge capaci ? ? ? tion ? ? ? ? ? signal area active devia standard area active * 100 u global units: %rms active area signal = active area av erage ? horizontal overclock average to peak this test is performed with the light source illuminated to a level such that the output of the sensor is at 70% of uration (approx st being performed the substrate voltage has been set such that the charge capacity of the sensor is 520mv. the sensor is partitioned into 100 sub regions of interest, each of which is of interest . the average signal leve l of each of the 100 su alculated. the signal level of each of the sub regions of interest is calculated using rizo ntal overclock average in adu) * mv per count n on the 100 sub regions of interest, the maximum and minimum signal the global peak to peak uniformity is then calculated as: = niformity 4. global peak uniformity sat imately 364 mv). prior to this te 100 by 100 pixels in size. see figure 1: test sub regions b regions of interest (roi) is c the following formula signal of roi[i] = (roi average in adu ? ho where i = 1 to 100. during this calculatio levels are found. signal area active signal minimum - signal maximum uniformity global = units: %pp c age has been set such that y of the sensor is 520mv. defects are ex cluded for the calculation of this test. this test is performed on the center 100 by 100 pixels (see test regions of interest and figure 3: center region of interest) of the sensor. center uniformity is defined as: 5. enter uniformity this test is performed with the light source illuminated to a level such that the output of the sensor is at 70% of aturation (approximately 364 mv). prior to this test being performed the substrate volt s the charge capacit ? ? ? ? ? ? ? signal roi center center roi signal = cent er roi average ? horizo ntal overclock average ? = deviation standard roi center * 100 uniformity roi center units: %rms f n 6. d ark field defect test this test is performed under dark field conditions. the sensor is partitioned into 100 sub regions of interest, each o which is 100 by 100 pixels in size. see figure 1: test sub regions of interest . in each region of interest, the media value of all pixels is found. for each regi on of interest, a pixel is marked defectiv e if it is greater than or equal to the m edian value of that region of interest plus the defect threshold specified. ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p19
7. bright field defect test this test is performed with the light source illuminated to a level such that the output of the sensor is at 70% of saturation (approximately 364 mv). prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 5 20mv. the average signal level of all a cti ve pixels is found. the bright and dark thresholds are set as: dark defect threshold = acti ve area signal * threshold bright defect threshold = ac tive area signal * threshold sub regions of in terest, each of which is 100 by 100 pixels in size. see figure . in each region of interest, the average value of all pixels is found. for each region of ian of this region of interest is found to be 366 mv. any pixel in this region of interest that is >= (366+40mv) 406mv in intensity will be marked defective. (366- 40mv) 324mv in intensity will be marked defective. ? all remaining 99 sub regions of interest are analyzed for in the same manner. r defect test al * threshold the sensor is then partitioned into 2500 sub regions of interest, each of which is 20 2 e. in each region of interest, the average value of all pixels is found. for each region of interest, a pixel is marked defective if it is less than or equ specified. example for bright field minor defective pixels: value of all active pi xels is found to be 365 mv. mv in intensity will be marked defective. ? all remaining 2499 sub regions of interest are anal yzed for defective pixels in the same manner. 9. bright field column average magnitude test this test is performed with the light source illuminated to a level such that the output of the sensor is at 70% of saturation (approximately 364 mv). prior to this test being performed the substrate voltage has been set such that the charge capacity of the sensor is 520 mv. a column is marked as defective if the sensor is then partitioned into 100 1: test sub regions of interest interest, a pixel is marked defective if it is greater than or equal to the median value of that region of interest plus the bright threshold specified or if it is less than or equal to the median value of that region of interest minus the dark threshold specified. example for major bright field defective pixels: ? average value of all active pi xels is found to be 365 mv. ? dark defect th reshold: 365mv * 11% = 40mv ? bright defect threshold: 365mv * 11% = 40mv ? region of interest #1 selected. this region of interest is pixels 1,1 to pixels 100,100. o med o o any pixel in this region of interest that is <= defect ive pixels 8. bright field mino this test is performed with the light source illuminated to a level such that the output of the sensor is at 70% of saturation (approximately 364 mv). prior to this test being performed the substrate voltage has been set such that the charge capacity of the sens or is 520mv. the average signal level of all active pixels is found. the dark thresholds is set as: dark defect threshold = acti ve area sign by 0 pixels in siz al to the median value of that re gion of interest minus the dark threshold ? average ? dark defect threshold: 365mv * 5% = 18mv ? region of interest #1 selected. this region of interest is pixels 1,1 to pixels 20,20. o median of this region of interest is found to be 366 mv. o any pixel in this region of interest that is <= (366- 18mv) 348 4.0 *100 > ? ? ? ? ? ? ? ? x) lumn avg(avg(co x) lumn avg(avg(co - n) avg(column abs where x=n-2 to n+2 ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p20
test regions of in terest test r total numb numb active a cente r 49 column only t test s egions of interest number of pixels: 1028 (h) x 1008 (v) er of photo sensitive pixels: 1004 (h) x 1004 (v) er of active pixels: 1000 (h) x 1000 (v) rea roi: pixel 1,1 to pixel 1000,1000 oi: pixel 450,450 to pixel 549,5 r magnitude test roi: pixel 11,11 to pixel 990, 990 he active pixels are used fo r performance and defect tests. see figure 2: regions of interest ub regions of interest pixel (1000,1000) pixel (1,1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 91 92 93 94 95 96 97 88 89 98 99 90 100 figure 1: test sub regions of interest ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p21
signal level calculation signal levels are calculated by using th e average of the region of interest under test and subtracting off the horizontal such that the sensor is overclocked in both the vertical and ation of the regions. following calculation used: (active lock average) * mv per count overclock region. the test system timing is configured horizontal directions. se a pictorial represent e figure 2 for example: to determine the active area average in m illivolts, the active area signal (mv) = area average ? horizontal ove rc pixel 1,1 vertical overclock horizontal overclock 2 buffer rows 2 buffer rows 2 buffer rows 2 buffer rows 12 dark rows 12 dark rows 4 dark rows vout1 figure 2: regions of interest ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p22
center region of interest 1000,1000 1,1000 1,1 1000,1 450,450 549,549 figure 3: center re gion of interest ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p23
zones 1 and 2 zone 2 includes zone 1 1,1 1000,1 1000,1000 1,1000 500 980 zone 2 zone 1 figure 4: zones 1 and 2 ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p24
operation single or dual output zero dark rows 12 dark columns 12 dark columns 4 dark rows 1004 x 1004 photoactive pixels zero dark rows 12 dark columns 12 dark columns 4 dark rows 1004 x 1004 photoactive pixels 502 8 1004 502 8 8 video 1 video 1 video 2 12 12 12 12 the kai-1020 is designed to read the image out o output at 30 frames/second or two outputs at 48 frames/second. in the dual outp ut mode the right half of the horizontal shift register reverses its direction of charge transfer. the left half of the image is read out of video 1 and the right half of th e image is read out of video 2. are no dark reference rows at the top and 4 dark rows at the bottom of the image sensor. the 4 dark rows should not be used for a dark reference level. the dark rows will contain smear signal from bright light sources. use the 12 dark columns on the left or right side of the image sensor as a dark reference. f one there ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p25
the kai-1020 pixel the pixel is 7.4 m square. it consists of a light sensitive photodiode and an optically shielded vertical shift register. the vertical shift register is a charge-coupled device (vccd). each pixel is covered by a microlens to increase the light gathering efficiency of the photodiode. under normal operation, the image capture process begins with a 4 s long pulse on the electronic shutter trigger input sh. the electronic shutter empties all the photodiodes start collectin g light on the falling edge of the sh pulse. for each photon that is incident upon the 7.4 m square area of the pixe l, the probability of an electron being generated in the photodiode is given by the quantum efficiency (qe). at the end of the desired integration time, a 10 s pulse on v2b transfers the charge (electrons) collected in the photodiode into the vccd. the integration time ends on the falling edge of v2b. charge from every photodiode in the pixel array. ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p26
high level black diagram hccd vccd phase 1 driver vccd phase 2 driver fast dump driver electronic shutter driver v1 sh v2a v2b fd pixel array substrate cds 1 t1 r1 s1a s1b vout1a vout1b cds 2 t2 r2 s2a s2b vout2a vout2b h2s h1br h2br h1s h1bl h2bl kai-1020 drivers control the shifting of charge through the vccd. the phase 2 driver also controls the transfer of charge from the photodiodes to the vccd. there is an integrated fast dump driver, which allows an entire row of pixels to be quickly discarded without clocking the row through the hccd. hotodiode on the image sensor. each of the two outputs has a correlated double sampling circuit to simplify the analog signal processing in the camera. the horizontal clock timing selects which outputs are active. an integrated electronic shutter driver generates a >30 volt pulse on the substrate to simultaneously empty every p all timing inputs are driven by 5v logic. the image sensor has integrated clock drivers to generate the proper voltages for the internal ccd gates. there are two vccd clock drivers. both the phas e 1 and phase 2 vccd ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p27
?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p28 main timing vertical frame timing horizontal line timing repeat for 1008 lines vertical frame timing t vccd 0 5 0 5 0 5 5 v2b h1s 0 5 0 v1 v2a h2s t vp t vp t v3
the vertical frame the image sensor timing may begin once the last pixel of has been read out of the hccd. the beginning of the vertical frame timing is at the rising edge of v2a. after the rising edge of v2a there must be a delay of t vp s before a pulse of t v3 s on v2b and v1. the charge is transferred from the photodiodes to the vccd during the time t v3 . the falling edge of v2b marks the end of the photodiode integration time. after the pulse on v2b the v1 and v2a should remain idle for t vp s before the horizontal line timing period begins. this allows the clock and well voltages time to settle for efficient charge transfer in the vccd. all hccd and cds timing inputs should run continuously through the vertical frame timing period. for an extremely short integration time , it is allowed to place an electronic shutter pulse on sh at any time during the vertical frame timing. the sh and v2b pulses may be overlapped. the integration time will be from the falling edge of sh to the falling edge of v2b. horizontal line timing 522 pixels 522 pixels video 2 h1s h2s h1bl h2bl h2br h1br kai-1020 hccd timing inputs ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p29
t v 0 5 0 5 when the v2a and v1 timing inputs are pulsed, charge in every pixel of the vccd is shifted one row towards the hccd. the last row next to the hccd is shifted into the ccd. when the vccd is shif ted, the timing signals to the hccd must be stopped. h1s must be stopped in the high state and h2s must be stopped in the low state. the hccd clocking may begin t vccd s after the falling edge of the v2a and v1 pulse. the timing inputs to the cds should run continuously through the horizontal line timing. the hccd has a total of 1036 pixels. the 1028 vertical shift registers (columns) are shifted into the center 1028 pixels of the hccd. there are 8 pixels at both ends of the hccd which receive no char ge from a vertical shift register. the first 8 clock cycles of the hccd will be empty pixels (containing no electrons). the next 12 clock cycles will contain only el ectrons generated by dark current in the vccd and photodiodes. the next 1004 clock cycles will contain phot o-electrons (image data). finally, the last 12 clock cycles will contain only electrons generated by dark current in the vccd and photodiodes. of the 12 dark columns, the first and last dark columns should not be used for determining the zero signal level. some light does leak into the first last dark columns. only us e the center 10 columns o 12 column dark reference. when the hccd is shifting valid image data, the timing inputs to the electronic shutter driver ( sh), vccd driver ( v2a, v2b, v1), and fast dump drivers ( fd) should be held at the low level. this prevents unwanted noise from being introduced into the cds circuit. the hccd is a type of charge coupled device known as a pseudo-two phase ccd. this type of ccd has the ability to shift charge in two direct ions. this allows the entire image to be shifted out to th e video 1 output cds, or to the video 2 output cds (left/right image reversal). the hccd is split into two equal halves of 522 pixels each. when operating the sensor in single output mode the two halves of the hccd are shifted in the same direction. when operating the sensor in dual output mode the two halves of the hccd are shifted in opposite directions. the direction of charge transfer in each half is controlled by the h1bl, h2bl, h1br, and h2br timing inputs. h and f the ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p30
single output to direct all pixels to the video 1 output make the following hccd connections: h1s = h1bl, h2br h2s = fh2bl, h1br to direct all pixels to the video 2 output make the following hccd connections: h1s = h2bl, h1br h2s = fh1bl, h2br in each case the first 8 pixe ls will contain no electrons, followed by 12 dark reference pixels containing only electrons generated by dark current, followed by 1004 photo-active pixels, followed by 12 dark reference pixels. the hccd must be clocked for at least 1028 cycles. the vccd may be clocked immediately after the 1028th hccd clock cycle. if the sensor is to be permanently operated in single output mode through video 1, then vdd2 (pins b8, and b10) may be connected to gnd. this disables the video 2 dual output to use both outputs for faster image readout, make the following hccd connections: h1s = h1bl, h1br h2s = h2bl, h2br for both outputs the first 8 hccd clock cycles contain no electrons, followed by 12 dark reference pixels containing only dark current electrons, followed by 502 photo-active pixels. this adds up to 522 pixels, but the hccd should be clocked for at least 523 cycles before the next vccd line shift takes place. the extra hccd clock cycle ensures that the signal from the last pixel exits the cds circuit before the vccd drivers switch the gate voltages. this extra cy cle is not needed for the single output modes because in that case, the last pixel is from a column of the dark reference which is not used. see the section on correlated double sampling for a description of the one pixel delay in the cds circuit. cds and lowers the power consumption. if the sensor is to be permanently operated in single output mode through video 2, then vdd1 and vdd2 supplies must be +15 v. the vdd1 supplies must always be at +15 v for the sensor to operate properly. ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p31
electronic shutter trate, pins l1 and l5, determines the charge capacity of the photodiodes. when vsub is 8 ill be at their maximum charge apacity. increasing vsub above 8 volts decreases the charge capacity of the photodiodes until 30 volts when ub, with a peak amplitude reater than 30 volts, empties all photodiodes and electronic shuttering action. ntiblooming the vsub voltage is set such that the bright spot is apacity is greater than the photodiode capacity. there are cases where an extremely bright spot will still cause blooming in the vccd. normally, when the photodiode is full, any additional electrons generated by photons will spill out of the photodiode. the excess electrons are drained harmlessly out to the subs trate. there is a maximum rate at which the electrons can be drained to the substrate. if that maximum rate is exceed ed, (say, for example, by a very bright light source) then it is possible for the total amount of charge in the photodiode to exceed the vccd capacity. this results in blooming. the amount of antiblooming protection also decreases when the integration time is decreased. ompromise be tween photodiode dynamic sub) and the amount of and minimum (or no) ntibloo ing protection. a high vsub voltage provides and maximum antiblooming setting of vsub is written on the int is desired, then the substrate voltage of the sensor is pulsed to at least 30 volts t int seconds before the photodiode to vccd transfer pulse on v2b. the large substrate voltage pulse is generated by the kai-1020. the electronic shutter is triggered by a 5 volt pulse on sh. use of the electronic shu tter does not have to wait until the previously acquired image has been completely read out of the vccd. the electronic shutter pulse may be added to the end of the horizontal line timing and just after the last pixel has been read out of the hccd. h1s and h2s must be clocked during the electronic shutter pulse. substrate voltage the voltage on the subs volts the photodiodes w c the photodiodes have a charge capacity of zero electrons. therefore, a short pulse on vs g provides the substrate voltage and a it may appear the optimal substrate voltage setting is 8 volts to obtain the maximum charge capacity and dynamic range. while setting vsub to 8 volts will provide the maximum dynamic range, it will also provide the minimum antiblooming protection. the kai-1020 vccd has a ch arge capacity of 60,000 electrons (60 ke). if photodiode holds more than 60 ke, then when the charge is transferred from a full ph otodiode to vccd, the vccd will overflow. this overflow condition manifests itself in the image by making bright spots appear elongated in the vertical direction. the size increase of a called blooming when the spot doubles in size. the blooming can be eliminated by increasing the voltage on vsub to lower the charge capacity of the photodiode. this ensures the vccd charge c there is a c range (controlled by v antiblooming protection. a low vsub voltage provides the maximum dynamic range a m lower dynamic range protection. the optimal container in which each kai-1020 is shipped. the given vsub voltage for each sensor is selected to provide antiblooming protection for bright spots at least 100 times saturation, while maintaining at least 500 mv of dynamic range. a detailed discussi on of antiblooming and smear may be found in ieee transactions on electron devices vol. 39 no. 11, pg. 2508. electronic shutter timing the electronic shutter provides a method of precisely controlling the image exposure time without any mechanical components. if an integration time of t ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p32
0 5 0 5 0 5 5 0 0 5 t vccd 0 fast dump the kai-1020 has the ability to rapidly discard (fast dump, to the last row of the vccd just before the hc cd. when vccd goes into the drain instead of into the hccd. fd) entire lines of the image. the fast dump is a drain attached the fast dump is activated by taking fd high, charge from the ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p33
0 5 0 5 0 5 0 5 0 5 0 5 ram shows how two lines are dumped read out. fd should go high once the ped. when the proper number of rows have been dumped bring fd low. then clock the vccd through one more cycle to shift a row into the hccd. the fast dump can be used to sub-sample the image for increased frame rates. for example, by dumping the even numbered lines, the image will be sub-sampled by a factor of 2 and the frame rate will almost increase by a factor of 2. horizontal sub-sampling is not possible. the hccd must always be cycled for the entire number of pixels in one line. another way to increase the frame rate is through sub- windowing. for example, suppose only the center 512 dump and clock the vccd (and hccd) for 512 lines. finally, turn the fast dump on again and clock the vccd for 240 lines. this timing diag and the third is last pixel of the preceding line has been read out. cycle the vccd for the number of rows to be dumped. the above timing diagrams shows two rows being dum lines of the image are needed. turn on the fast dump and clock the vccd for 256 lines. then turn off the fast ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p34
binning and interlaced modes binning is a readout mode of progressive scan ccd image sensors where more th an one row at a time is clocked into the hccd before reading out the hccd. this timing mode sums two or more rows together. it increases the frame rate b ecause there are fewer total rows to read out of the hccd. the following timing diagram shows how two rows are summed together: when binning two rows together only 504 rows need to be read out of the hccd instead of the normal 1008 rows. the hccd will hold up to two vccd rows of full signal without blooming. binning more than two rows may cause horizontal blooming for saturated signal levels. interlaced readout is a form of binning. to read out the even field use binning to sum together rows 0+1, rows 2+3, ... rows 1006+1007. to read out the odd field use binning to read out rows 0+1+2, rows 3+4, rows 5+6, .... rows 1005+1006, rows 1007+1008. the odd field may also be read out as row 0, rows 1+2, rows 3+4, .... rows 1005+1006. see the interlaced ? field integration section for an example of interlaced timing. 0 5 0 5 0 5 t vccd 0 5 h1s h2s v1 v2a t vccd t p t vccd t vccd 0 5 0 5 v2b fd ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p35
correlated double sampling (c ds) r sa sb t vouta voutb hccd vref c sa c sb c tb output c c ta vdd vd d correlated double sampling is a method of measuring the amount of charge in each pixel. the electrons in the last pixel of the hccd are transferred onto a very small sensing capacitor, c, on the falling edge of h2s. the voltage on c will change by about 20 v for each electron that was in the hccd. the process of measuring the amount of charge begins by resetting the value of c to an internally generated reference voltage, vref. a short pulse on r at the rising edge of h2s will reset c. after c has been reset, its voltage is sampled and stored on c sa by a short pulse on switch sa. then on the falling edge of h2s, electrons are transferred onto the capacitor, c. the new voltage on c is sampled and stored on c sb by a short pulse on switch sb. these two sampled voltages are then transferred to capacitors c ta and c tb by a short pulse on t. t and r generally occur at the same time. an external operational amplifier is used to subtract the two voltages on vouta and voutb. the output of the op-amp will be proportional to the number of electrons contained in one pixel. note that it takes one entire pixel clock cycle for the value of the pixel to appear on vouta and voutb. the a and b outputs of the cds circuit will be in the range of 7 to 11 volts. cds timing edge alignment 1. the edge alignments of the cds timing pulses sa, sb, t, and r are critical to proper operation of the cds circuit. 2. the falling edge of r must not overlap the rising edge of sa 3. the falling edge of sa must come at the same time or before the falling edge of h2 4. the rising edge of sb must come after the falling edge of h2 5. the falling edge of sb must come before the rising edge of r 6. the rising edge of r may come before the rising edge of h2 7. t should always be driv en by the same timing signal as r 8. the pulse widths should be set such that r, sa, and sb are 1/3 of t p ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p36
t p 0 5 nt to use g to digital c d auto offset/gain circuits are processed nnecting them in the range of 8 to 10v (the v2high a on vouta a load may b stor and the 0.1ma load may be an d for pixel disabling the cds there may be instances when the camera de signer may wa frequencies 20mhz or slower where integrat ed cds, analo available. these external cds circuits require the raw un permanently turning on the sa, sb, and t switches by co supply voltage, for example). then place a load of 4ma to 5m raw video output suitable for external cds circuits. the 5m 80k resistor to gnd. an external cds is not recommende an external cd s. such cases may occur at pixel clock onverter (a /d), an video wavefo rm. the raw video can be obtained by to a voltag e and a load of 0.1ma on voutb. vouta will be the e a 2.0k resi frequencies above 20mhz. ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p37
timing and voltage specifications absolute maximum ratings min. max. units notes operation without damage -50 70 c temperature storage -55 70 c vsub to gnd 8 20 v 1 vdd to gnd 0 17 v v1 to v2, fd to v1, v2 -10 10 v h1 to h2 -8 8 v r, t, sa, sb to gnd -9 12 v voltage between pins h1, h2 to v1, v2 -9 10 v current video output bias current 0 7 ma 2 notes: 1. for electronic shuttering vsub ma y be pulsed to 35 v for up to 10 s. 2. note that the current bias effects the amplifier bandwidth. timing time min. nominal max. units t p 25 25 500 ns t vccd 3.6 3.6 10 s t vp 20 25 40 s t v3 8 10 15 s bias voltages bias min (volts) nominal (volts) max (volts) peak current (ma) peak current frequency avg. current (ma) v1s5 4 5 6 2 2l 0.13 v1mid -1.5 -1.2 -1.0 110 l 3 v1low -9.5 -9 -8.5 110 l 3 v2s5 4 5 6 2 2l 0.5 v2s9 8 9 10 2 f 0.3 v2high 8 9 10 110 l 0.01 v2mid -1.5 -1.2 -1.0 110 l 3 v2low -9.5 -9 -8.5 110 220 l f 3.8 vdd1 14.5 15 15.5 14 vdd2 14.5 15 15.5 14 vsh15 14 15 16 1 f 0.08 vsub 8 * 14 0.03 average currents are for 30 frames/second peak switching currents are for less than 1 s duration l = once per line time, 2l = twice per line time, f = once per frame time * substrate bias voltage for a 500mv output range is written on the shipping container for each part power up sequence 1. power up vsub, v1low, v2low first 2. then power up vdd, vsh15, v2s5, v1s5, v1mid, v2mid and v2high 3. then after the coupling capacitors on all of the timing inputs have char ged, begin clocking the timing inputs. any positive voltage should neve r be allowed to go negative. an y negative voltage should neve r be allowed to go positive. note that the shutter driver clock input does not use a coupling ca pacitor. it must be driven dire ctly from a 5v logic buffer a s shown in the evaluation board schematic. ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p38
pulse amplitudes sh 3.5 dc -- -- h1 4.7 ac 0. 0.1 47 h2 ac 0.1 0 4.7 .47 sa ac 1 0. 4.7 0.0 47 sb 4.7 ac 0. 01 0. 47 r 4.7 ac 1 0. 0.0 47 t 1 0. 4.7 ac 0.0 47 v1 1 0. 4.0 ac 0.0 47 v2a 4.0 ac 0.0 1 0 .47 v2b 4 0.01 0.4 .0 ac 7 f 4.0 ac 0.1 0.4 d 7 ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p39
timing exampl es progres sive scan v2b v2a v1 h1 h2 sh fd v2b v2a v1 h1 h2 sh fd progressive s can, no e lectronic shutter exposu e = frame time progressive scan, using electronic shutter re tim frame time exposure time repeat 1 imes move this pulse in increments of one line time to change the exposure time 008 t 1028 clock cycles single output 523 clock cycles dual output this line has 7.2 s more hccd clock cycles than all other lines ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p40
fast line dump v2b v2a v1 h1 h2 sh fd repeat 256 times repeat 252 times repeat 500 times fast dump timing, reads out the center 500 rows exposure time = frame time repeat 256 times repeat 252 times repeat 500 times frame time sh pulse width = 3.6 s, total interval = 7.2 s exposure time v2b v2a v1 h1 h2 sh fd fast dump timing with electronic shutter, reads out the center 500 rows 1028 clock cycles single output 523 clock cycles dual output ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p41
interlaced ? field integration v2b v2a v1 h1 h2 sh fd repeat 256 times repeat 252 times repeat 500 times fast dump timing, reads out the center 500 rows exposure time = frame time repeat 256 times repeat 252 times repeat 500 times frame time sh pulse width = 3.6 s, total interval = 7.2 s exposure time v2b v2a v1 h1 h2 sh fd fast dump timing with electronic shutter, reads out the center 500 rows 1028 clock cycles single output 523 clock cycles dual output ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p42
camera design low level block diagram ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p43
horizontal ccd drive circuit the hccd clock inputs shou ld be driven by buffers capable of driving a capacitan ce of 60pf and having a full voltage swing of at least 4.7 v. a 74ac04 or equivalent is recommended to drive the hc cd. the hccd requires a 0 to ?5v clock. a negative clock level is easily obtained by capacitive coupling and a diode to clamp the high level to gnd. every hccd clock input has a 300k on chip resistor to gnd. the inputs to the above circuits, h1 and h2, are 5v logic from the timing generator (a programmable gate array for example). if the camera is to have selectable single or dual output modes of operation, then the timing logic needs to generate two extr a signals for the h1br and h2br timing. for single output mode program the timing such that h1br=h2 and h2br=h1. for dual output mode program the timing such that h1br=h1 and h2br=h2. ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p44
vertical ccd the vccd clock inputs, v2a, v2b, v1, and fd have a capacitive load of approxim ately 10pf. each input is connected to v2low and v1low by a 60k internal resistor. there is also an internal diode connected to v2low and v1low. the 5v logic drivers must be connected to the sensor inputs through capacitors. these inputs requ ire a clock of at least 4 v amplitude. most pga's can drive these inputs directly. the exte rnal capacitor and internal diode level shift the 0v to 5v input to v2low to v2low + 5. the on chip vccd clock drivers switch their outputs, v1 out and v2out, between the supply voltages v1low, v1mid, v2low, v2mid, and v2high. the truth ta ble correlating the voltage on v1out and v2out to the timing inputs is: l v1mid h v1low l l v2low h l v2mid l h v2high h h v2high l = logic low level h = logic high level the output of the vccd driver is connected to the vccd gate s by wiring v1out to v1in and v2out to v2in. the fast dump driver has no external output. it is wire d internally to the vccd fast dump gate. ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p45
electronic sh utter by a trim-pot r2 or by so me programmable voltage source. the substrate bias voltage the electronic shutter input, sh, is the only input driven directly by cmos logic. no capacitive coupling is required. sh (pin b3) has approximately a 10pf load. the logic low level must be less than 0.5 v an d the logic high level must be greater than 3.5 v. most programmable gate arrays can drive sh directly. the on chip electronic shutter driver is a charge pumping circuit. it uses c1, c2, d1, and d2 to generate a >25v pulse that is added onto the substrate dc bias voltage. the substrate bias voltage is set absolutely must be adjustable. the camera designer can not rely on every kai-1020 image sensor requiring the same substrate bias. an adjustment range of 8 to 13v must be allowed. each image sensor has the optimal substrate bias voltage (as measured on the vsub pin) printed on the shipping container. t he minimum allowed voltage on vsub is 8 v. lower vo ltages may destroy the cds and clock driver circuits. ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p46
cds timing inputs the cds timing inputs r, t, sa, and sb should be driven by cmos logic with fast rise and fall times and an amplitude of at least 4.7 v. the capacitan ce of each pin on the sensor is approximately 10p f. the pulses are level shifted positive by 1 v or 2 v on the sensor. if driving this input directly from a pr ogrammable gate array, be aware that some pga's do not have outputs with amplitudes of 4.7v. it is recommended that the cds timing inputs be driven by a 74ac04 to insure a 5v pulse amplitude with fast edges. if the camera will only operate in single output mode then the r2, t2, s2a, and s2b inputs should be connected to gnd. all cds timing inputs must be coupled with a capacitor. cds output circuit in the above schematic the differential video outputs voutb an d vouta are subtracted by op-amp u2a. the video outputs will have a dc level of 7 to 11v. u2b then inverts the signal an d applies a gain of 2.1 relative to the offset voltage. the output of u2b will match the 500mv output range of the kai-1020 to the 1v input range of the analog to digital converter (a/d) ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p47
voutb will swing in the ne with increasing light level gative direction wi th increasing light level. the output of u2a will swing in the positive direction . the output of u2b (input to the a/d) will swing in the negative direction. this means the a/d reference columns and adjust the offset voltage of u2b to mainta in a constant zero reference level in the a/d converter. the dynamic adjustment of the of fset voltage will remove most temperature dependent drifts. small temperature-dependant gain change s will still be present. see the kai-1020 evaluation board schematic for and example of a circuit to generate the offset voltage. this output circuit provides 10 bits of dynamic range on the kai-1020 evaluation bo ard. it is not the optimum circuit. for optimum differential common mode noise rejection and linearit y, the cds output circuit should take into account the 160 impedance of the cds output drive transistor. power supplies output will be 0 counts when the image sensor is saturated. the digital data will have to be inverted before being transmitted to a digital image capture device. see the kai- 1020 evaluation board schematic for a simple method of inverting the data with no additional components. the offset will have to be dynamically ad justed to match the zero light level of the image sensor. a circuit should examine the digital data in the dark +15v vsh15(a3) vdd1(k8,l10) vdd2(b10,b8) +5v v2s5(l6) v1s5(b7) +9v v2high(l4) gnd v1mid(a7) v2s9(k6) v2mid(k4) 0.1u -9v v2high(k3) v1low(k6) d2 d4 the v1mid and v2mid connections must be set to ?1.0 to ?1. 5v. since v1mid and v2mid only sink current, two diodes can be used to set this voltage. if the sensor is to use only the single output mode, then vdd2(b10,b8) can be connected to gnd. vout2a(a9) and vout2b(a10) also should be connected to gnd in the single output only mode. ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p48
kai-1020 evaluation board front side pin 1 index ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p49
back side +5v gnd gnd +15v -15v power substrate voltage trim electronic shutter exposure control fast dump on fast dump off interlaced progressive 2 outputs 1 output ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p50
schematic s kai-1020 ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p51
timing logic ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p52
output 1 ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p53
output 2 ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p54
automatic offset and power supply ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p55
parts list c1 pcap, 4.7 f r1 vres,10k sw1 dip8 4 pos dip sw c2 cap, 0.1 f r2 res,470 sw2 dial 16 pos rotary c3 cap, 1 f r3 res,1k u1 kai1020 image sensor c4-9 cap, 0.1 f r7 res,20 u2 ad9042/so a/d analog dev c10 cap, 4.7 f r8 resnet u3 opamp dual,opa2650u burr brown c11, c12 cap, 0.1 f r9 res,100 u4 ad9042/so a/d analog dev c13-15 cap, 4.7 f r10, r11 res,1k u5 opamp dual,opa2650u burr brown c16 cap, 0.1 f r12 res,2k u6 ds90c031 national c17 cap, 1 f r13 res,1k u7 lm337l c18-21 cap, 0.1 f r14 resnet u8 lat1032e tqfp100 lattice semi c22 cap, 4.7 f r15 resnet u9 74ac04 c23, c24 cap, 0.1 f r16, r17 res,1k u10 delay10 data delay dev 711 2.5 ns c25 cap, 4.7 f r18 res,2k u11 74ac04 c26 cap, 0.1 f r19 res,1k u12 lat1016 lattice semi c27 cap, 4.7 f r20 res,470 u13 opamp-dual, lmc6492bem national c28 cap, 0.1 f r21 res,1k u14 osc\so 80 mhz c29 cap, 4.7 f r23 res,5.6k u15-20 ds90c031 national c30 cap, 0.1 f r24 res,2k u21 lm317l c31 cap, 4.7 f r25 res,20 u22, u23 nc7sz126 fairchild c32-38 cap, 0.1 f r26 res,2k l1-4 fb ferrite bead c39 cap, 4.7 f r27 res,100 j1 scsi-100 c40-52 cap, 0.1 f r28 resnet j2 header10 power conn c53-55 cap, 4.7 f r29 res,2k j3 sip\8p program conn c56-58 cap, 0.1 f r30 res,200 j4 latcon program conn c59 cap, 4.7 f r31 res,200 c60-63 cap, 0.1 f r32 res,1.24k c64 cap, 4.7 f r33 res,220 c65-72 cap, 0.1 f r34 res,1.24k d1-3 mmbd914 r35 res,220 d4, d5 mmbd2837 r36 res,1.5k r43 res,100k r44 res,200 r45 res,100k r46 res,200 ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p56
digital out put connector the ou t con p male c n r , pin compatible with the nation ci-1424 digital e gr mb 7766 in le fr om national in number 18501 . o in tp pin tpu nector is a 10 0 in fe scsi type o necto al instruments p struments, part fram abber, part n u er 7 2- 02. the terface cabl e is availab 2-02 utput 1 p ou u t 2 sync pin d ata 0+ 1 da ta 51 pixel + 0 + 49 d ata 52 ata 0- 2 d 0 - pixel - 50 d ata 53 line + ata 1+ 3 d 1 + 43 d ata 54 line - 44 ata 1- 4 d 1 - d ta 55 ame + ata 2+ 5 da 2 + fr 41 d ta 56 frame - 42 ata 2- 6 da 2 - d ata 3+ 7 d ata 57 field index 3 + 45 data 3- 8 data 3- 58 gnd 99 d ata 59 gnd ata 4+ 9 d 4 + 100 d ata 60 ata 4- 10 d 4 - d ta 61 ata 5+ 11 da 5 + d ata 62 ata 5- 12 d 5 - d ta ata 6+ 13 da 6 + 63 d ta ata 6- 14 da 6 - 64 d ata ata 7+ 15 d 7 + 65 d ata ata 7- 16 d 7 - 66 d ata 67 ata 8+ 17 d 8 + d ta 68 ata 8- 18 da 8 - d ta 69 ata 9+ 19 da 9 + d ata 70 ata 9- 20 d 9 - d ta 71 ata 10+ 21 da 1 0+ d ta 10- 72 ata 10- 22 da d 11+ 73 ata 11+ 23 data d ta 11- 74 ata 11- 24 da all other pins have no connection. all ou tputs are driven by low voltage differentia l line drivers (lvds) except for the field index which is t tl. ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p57
power connector +15 +15 gnd gnd -15 gnd +5 -15 gnd +5 0. 1" 0.1" the evaluation quire 15 v -15 v, an d +5 urre aw r each supply supply cur ) board re s + , v. the c nt dr fo is: rent (ma +15 62 -15 18 +5 780 mode switc switch on ff h o 1 fas ff ast dump on t dump o f 2 1 ou out uts tput 2 p 3 --- -- -- 4 progressive ter ced scan in la when the fast dump is activate d the timing dumps the first 256 lines, then re ads out 512 lines of image data, and finally it dumps the last 240 lines. the resulting image is 1000 colu mns by 512 rows. the interlaced mode timing is not programmed to support fast dumping. ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p58
exposure switch all exposure times are in s. electronic shuttering is not programmed in to the timing generator for interlaced mode. fd off fd on exposure setting 1 output 2 outputs 1 output 2 outputs 0 33300 20600 20600 14160 1 16400 10160 6000 4400 2 7960 4960 3000 2540 3 3740 2320 1860 1840 4 1616 1016 1700 1700 5 564 362 824 824 6 298 198 460 460 7 68 55 93 93 substrate voltage trim th s the substrate voltage to be varied from 0v to 15v. adju sting this voltage will change the charge capacity and anti-blooming of the pixel photod iodes. do not adjust the voltage below 8 v. evaluation board notes timing generated by a programmable gate array u8. the hccd drive is setup for selectable single or dual ou n ing the h2br a 2bl timing signal s depending on the setting of the mode switch sw1. the rt p t, generated by combining (logical and/or) the outputs of the delay line u10. each p on u10 delays th e sys y 2.5ns. the amount of noise in the kai1020 will ha ve a strong dependence on the stability of the timing inputs. the most sensitive inpu re c puts. the evaluation board uses one pga (u8) to hold all of the counters and to enerate the cds timing. this is not the optimum arrangement. though gray code counters were used, some fixed pattern hccd gating signal to a second pga. the second pga would ou tput the hccd clock as well as form the cds timing pulses om the multi-tap delay line u10. this second pga would contain no counters. is variab le resistor allow the main timing is tput by i vert nd h sho ulses for r, sa, and sb are ta tem clock b ts a the hccd and the ds timing in g column noise can be seen in the image fr om the counters inside u8. the counters inside u8 cause small disturbances of the hccd and cds timing. one solution to eliminate this noise source is to separate the counters and cds pulse generation into two separate pga's. one pga would contain all of the counters for the ro ws and columns, and send a fr ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p59
output channel the output circuit is identical to sectio n 0. the two op-amps u5a an d u5b present an inverted signal to the adc u4 . the offset circuit will maintain the digital output of u4 at 4080 when the image sensor is in the dark. the output of u4 will be t e sensor is sat with light. the digital data is inverted by swapping the high and low outputs of the ial s p t tomatic o 2 is used to control the auto matic offset circuit. u8 sends a signal to u 12 on the line blklev when the output of the alog to d onve orres to th ter 10 columns of the kai1020 dark reference. when u12 receives the nal from 12 co s the ts o /d converte rs to the number 4080. if the output is above or below 4080, 2 enable buffe 2 and d se eir inputs to cause the integrator s u13a and u13b to raise or lower the set voltag ate monitor the output of the a/ d converters. this function shou ld not be combined with u8 en the digital data will cause noise in the timing outputs to the image sensor. this puts are near a major bit boundary, such as 2048 or 1024. at these bit boundaries there age because the offset changes offs et circuit would measure the offset error along the entire column and then correct zero when he imag urated different line driver on the out ut connec or. au ffset u1 an igital c rter c ponds e cen sig u8, u mpare outpu f the a u1 s the rs u2 u23 an ts th off es. a separ pga (u12) is used to into one pga. if only one pga is used th is especially true when the a/d out are a large number of bits changing value that woul d disturb the stability of the hccd and cds clocking. the automatic offset updates the offset every line. this does cause some noise in the im slightly each line time. an improved the offset voltage once per frame. ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p60
oscilloscop e traces this section contains oscillosco pe traces of signals measured on the kai1020 pins. some of the timing signals are not 0 to 5v because the kai1020 has level shifte d the signals. all signals were measured on the kai1020 evaluation board. cds timing kai-1020 40 mhz timing -6 -4 -2 8 10 0 2 volt 4 6 s h2s r sb sa 0 5 10 15 20 25 30 35 40 45 50 time (ns) ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p61
vertical retrace kai1020 vertical retrace -10 -8 -6 -4 -2 0 2 4 6 8 10 volts v2out v1out -10 -8 -6 -4 -2 0 -10 0 10 20 30 40 50 60 70 80 90 time (s) volts v2b v1 v2a ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p62
horizontal retrac e kai1020 horizontal retrace -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 volts v1out v2out -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 - 1012345678 time (s) volts h1s v1, v2a ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p63
storage and h andling esd 1. this device contains limited protection against electrostatic discharge (esd). ccd image sensors can be damaged by electrostatic discharge. failure to do so may alter device pe rformance and reliability. 2. devices should be handled in accordance with strict esd procedures for class 0 (<250v per jesd22 human body model test), or class a (<200v jesd22 machine model test) devices. 3. devices are shipped in static-safe containers and should only be handled at static-safe workstations. 4. see application note mtd/ps-0224 ?electrostatic discharge control for image sensors? for proper handling and grounding procedures. this application note also contains reco mmendations for workplace modifications for the minimi zation of electrostatic discharge. 5. store devices in containers made of electro- conductive materials. cover glass care and cleanliness 1. the cover glass is highly susceptible to particles and other contamination. perform all assembly operations in a clean environment. 2. touching the cover glass must be avoided 3. improper cleaning of the cover glass may damage these devices. refer to application note mtd/ps- 0237 ?cover glass cleaning for image sensors? environmental exposure 1. do not expose to strong sun light for long periods of time. the color filters and/or microlenses may become discolored. long time exposures to a static high contrast scene should be avoided. the image sensor may become discolored and localized changes in response may occur from color filter/microlens aging. 2. exposure to temperatures exceeding the absolute maximum levels should be avoided for storage and operation. failure to do so may alter device performance and reliability. 3. avoid sudden temperature changes. 4. exposure to excessive humidity will affect device characteristics and should be avoided. failure to do so may alter device performance and reliability. 5. avoid storage of the product in the presence of dust or corrosive agents or gases. long-term storage should be avoided. deterioration of lead solderability may occur. it is advised that the solderability of the device lead s be re-inspected after an extended period of storage, over one year. ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p64
mechanical drawings comp leted assembly pin grid array ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p65
leadless chip carrier leadless chip carrier and soldering care should be taken when using reflow ovens to solder the kai-1020 to circuit boards. extreme temperatures may cause degradation to the color filt ers or microlens material. ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p66
cover glass pin grid array cover glass .709 .002 [18.01 .05 ] .551 .010 [14.00 .25 ] .030 .002 [.76 .05 ] . 0 2 0 [ r . 5 1 ] ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p67
leadless chip car rier cover glass ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p68
glass transmission kai-1020 glass transmission 0 10 20 30 40 50 60 70 80 90 100 200 300 400 500 600 700 800 900 wavelength (nm) transmission (%) kai1020 ar glass a r coated used on both package configurations ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p69
quality assurance and reliability quality strategy all image sensors will conform to the specifications stated in this document. this will be accomplished through a combination of statistical process control and inspection at key points of the production process. typical specification limits are not guaranteed but provided as a design target. for further information refer to iss application note mtd/ps-0292, quality and reliability. replacement all devices are warranted agai nst failure in accordance with the terms of terms of sale. this does not include failure due to mechanical an d electrical causes defined as the liability of th e customer below. liability of the supplier: a reject is defined as an image sensor that does not meet all of the specifications in this document upon receipt by the customer. liability of the customer damage from mechanical (s cratches or breakage), electrostatic discharge (esd) damage, or other electrical misuse of the device beyond the stated absolute maximum ratings, which occurred after receipt of the sensor by the customer, shall be the responsibility of the customer. reliability information concerning the quality assurance and reliability testing procedures and results are available from the image sensor solutions and can be supplied upon request. for further information refer to iss application note mtd/ps-0292, quality and reliability. test data retention image sensors shall have an identifying number traceable to a test data file. test data shall be kept for a period of 2 years after date of delivery. mechanical the device assembly drawing is provided as a reference. the device will conform to the published package tolerances. kodak reserves the right to change any in formation contained herein without notice. all information furnished by kodak is believed to be accurate. warning: life support applications policy kodak image sensors are not authorized for and should not be used within life support systems without the specific written consent of the eastman kodak comp any. product warranty is limited to replacement of defective components and does not cover injury or property or other consequential damages. ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p70
revision changes number description of changes revision 0.0 ? original formal ver sion. 1.0 ? correct vs29 connection to 9 volt supply, not 15 volt supply in sc hematic on page 42. ? added revision changes 2.0 ? added section 1.3.5 general ? color ? added section 1.4.2 color quantum efficiency ? added section 1.4.3 color filter array pattern ? updated section 2.2.1 pin grid array package drawing ? added section 2.2 leadless chip carrier package ? added section 3 glass ? section 5.6 changed ?dc level of 7 to 9c? to ?dc level of 7 ? section 6.5 parts list to 11v u13: corrected from opamp-dual lm 649bem to lmc6942be u22, u23: corrected from ncsz126 to nc7sz126 ? m 3.0 ? updated ? section numbe page layout. rs removed. and row ns and r rt configurations. ? updated section 3.1 pin grid array package cover glass. glass lear to mar.updated section 3.3 glass transmission. changed v1mid and v2 mid from ? updated drawing in section 1.2 to show buffer columns ? updated section 1.4.1 monochrome quantum efficiency. ? updated section 1.4.3 cf a pattern to show buffer colum ? updated section 1.9 quality assurance and reliability. ? added section 1.10.1 available pa s. ows. ch anged from c ? section 4.11.2 bias voltages, min ?1.5, nom ?1.0 , max ?0.5 to min ?1.5, num ?1.2, max ?1.0 ? section 4.11.2 added power up sequence note. 4.0 ? corrected figure ? corrected figu on page 4. buffers rows and columns were incorrect. changed from 4 rows/columns to 2 rows/columns. re on page 8. buffers rows and columns were incorrect. changed from 4 rows/columns to 2 rows/columns. 4.1 ? page 5 ? added to the cds o ? page 36 correlated double sa utput specifiction table an output bias current nominal value. mpling (cds) section ? last sentence changed from ?the a and b outp uts of the cds circuit will be i n the circuit will be in the range of 7 to 11 volts.?. this matches the ch ange made in mid and v2mid power supply. corr ected sentences below schematics from ?the v. since v1mid and v2mid only sink current, one diode can be used to set this set to ?1.0 to ?1.5v. since v1mid and v2mid only sink current, two diodes can update in revision 3.0. ts the v1mid and v2mid voltage to ?1.2v. range of 7 to 9 volts.? to ?the a and b outputs of the cds revision 2.0. ? page 48 ? updated schematic to show two di odes for v1 v1mid and v2mid connections must be set to ?0 .6 to ?1.5 voltage.? to ?the v1mid and v2mid connections must be be used to set this voltage. this change is to match the ? page 51 ? updated schematic ? addi tion of d4, which se 5.0 ? updated format ? updated pictures on summ ary specification page ? added sampling plan to performance parameters ? update evaluation board pictures ? merged mtd-ps-0293 kai-1020 test supplement specification into this document ?eastman kodak company, 2007 www.kodak.com/go/imagers revision 5.0 mtd/ps-0205 p71
?eastman kodak company, 20 06 . kodak and pixelux are trademarks.

▲Up To Search▲

Price & Availability of KAI-1020-CBA-FD-BA

	To Download KAI-1020-CBA-FD-BA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .